`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:46:00 05/02/2010 
// Design Name: 
// Module Name:    addr_mux 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module addr_mux(
    input [9:0] addr_in0,
    input [9:0] addr_in1,
    input sel,
    output [9:0] out
    );

assign out[0] = (addr_in0[0] & ~sel) | (addr_in1[0] & sel);
assign out[1] = (addr_in0[1] & ~sel) | (addr_in1[1] & sel);
assign out[2] = (addr_in0[2] & ~sel) | (addr_in1[2] & sel);
assign out[3] = (addr_in0[3] & ~sel) | (addr_in1[3] & sel);
assign out[4] = (addr_in0[4] & ~sel) | (addr_in1[4] & sel);
assign out[5] = (addr_in0[5] & ~sel) | (addr_in1[5] & sel);
assign out[6] = (addr_in0[6] & ~sel) | (addr_in1[6] & sel);
assign out[7] = (addr_in0[7] & ~sel) | (addr_in1[7] & sel);
assign out[8] = (addr_in0[8] & ~sel) | (addr_in1[8] & sel);
assign out[9] = (addr_in0[9] & ~sel) | (addr_in1[9] & sel);

endmodule
